1. Field of Invention
The present invention relates to a logic circuit and, particularly, to a complementary energy path adiabatic logic (CEPAL) capable of improving reliability and energy efficiency and increasing the throughput thereof.
2. Description of Related Art
The conventional reversible adiabatic logic has a control signal feedback from the next stage thereof. Thus, design cost for large systems using such logic is expensive. Although an irreversible adiabatic logic has the advantage of not needing use of the next-stage control signal in implementation, almost all such circuits have the characteristics of dynamic circuit and the problem of relatively higher switch activities, which are related to a ratioed logic. In addition, most of the irreversible adiabatic logic circuits have the requirements of multi-phase and multi-clock, making use not favorable to circuit designers in terms of design complexity and required area for realization. In response to that, a quasi-static energy recovery logic (QSERL) circuit has been suggested to overcome the shortcomings of the irreversible logic circuit above mentioned. The conventional QSERL circuit mainly comprises an evaluation network and a power clock network. The power clock network comprises a diode-connected P-type metal-oxide-semiconductor (MOS) transistor, a diode-connected N-type MOS transistor and two power clocks (or two diodes and two power clocks). The evaluation network is a logic circuit combined with P and N-type MOS transistors. In operation, the evaluation network follows the two inputted power clocks to perform evaluation and operation jobs.
As shown in FIG. 7, the power clock network has MOS transistors QP1, QN1, QP2 and QN2, and four inverting circuits work with the power clock network to jointly realize a QSERL inverter chain with the MOS transistors QPI, QN1, QP2 and QN2. The inverter chain is formed by four cascaded stages of inverters. In the inverter chain, the first, second, third and four-stage inverters are composed of MOS transistors MP5 and MN5, MP6 and MN6, MP7 and MN7, and MP8 and MN8, respectively. This QSERL has simple and static logic-like characteristics, lending itself to have considerably reduced design complexity and switch activity. The design with the complementary power clocks has higher energy efficiency as compared with the prior art having more clocking phases. However, such QSERL has to alternatively maintain a “hold” phase, causing the output to be floated in operation and, thus, has the reliability issue regarding the operational correctness to be considered. Although this problem can be overcome by introducing an additional feedback keeper controlled by additional clocking signals into each of the QSERLs, energy efficiency is correspondingly reduced. Furthermore, the required implementation area and overhead for the additional keepers and the control signals may considerably limit the QSERL's applications. As may be seen from above, the conventional adiabatic logic still has problems to be solved and, thus, has to be improved.